S-CORE v1.0 Roadmap

This document describes the release planning for S-CORE v1.0, structured around the eclipse-score/score milestones. It is structured around two overarching project goals:

1. Feature Completeness — Selected modules are fully implemented and tested.

Module	Notes
Baselibs	Base libraries (C++)
Baselibs Rust	Base libraries (Rust)
Communication	IPC / service-oriented communication
Logging	Platform logging
Persistency	Data persistence
Time	Time services
Config Management	Configuration management
Lifecycle	Lifecycle management
Security/Crypto	Cryptographic services
Diagnosis	On-board diagnostics / DTC management
Some/IP	SOME/IP communication middleware

2. Qualifiable State

All modules follow the S-CORE process and use S-CORE tools for artifact generation across the following process areas:

Process Area	Definition
PA2 — Requirements Engineering	Requirements Engineering
PA3 — Architecture Design	Architecture Design
PA4 — Implementation	Implementation
PA5 — Verification	Verification

Note

We will also work on the other process areas, but they are not in the main focus for S-CORE v1.0.

Status & Goals

• Overall Status
• PI 1 — Requirements Engineering + Architecture Design
• PI 2 — Implementation
• PI 3 — Verification
• PI 4 — Hardening & Release