mw::log Backend Detailed Design#
mw::log Backend Detailed Design
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status: draft
security: YES
safety: ASIL_B
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Description#
The mw::log backends are selected in two steps (see
mw::log Backend (Static View) (comp_arc_sta__log__sv)). At build time, the application links the
backends it needs. Each linked backend registers itself for a LogMode
before main() (backend/*_registrant.cpp). At runtime, the logging
application configuration selects the LogMode values and a recorder is
created for each of them that has a registered backend. The recorders and
backends are shown in the static diagram below.
The design documents and PlantUML diagrams are in
score/mw/log/design/backend. This folder links them by symbolic links, so
that the files stay at their place in the source tree. The
architectural_design target //score/mw/log/design/backend:mw_log_backend_architectural_design
validates the diagrams.
Design Decisions#
The diagrams show how the design addresses the requirements and concerns.
Requirement or concern |
Diagram |
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New outputs only need a new backend: recorder and backend are separate abstractions |
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Backends are independent of the log record format |
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Local allocation of the log slots (Local Allocation Strategy (comp_req__log__local_allocation_strategy)) |
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A logging call does not block (Avoid Locks (comp_req__log__avoid_locks)) |
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Unit tests without real OS resources |
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Lock-free logging and freedom from interference with the Datarouter |
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No leaked shared memory file |
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The frontend does not depend on the backends |
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Design decisions that need a formal record use gd_temp__change_decision_record; see also Explicit initialization of ... (dec_rec__logging__explicit_init).
Design Constraints#
All requirements of the component apply, see mw::log Backend Component R... (doc__mw_log_backend_requirements). The diagrams show the constraints per building block.
Building block |
Constraint |
Diagram |
|---|---|---|
All units |
Local allocators instead of the global heap, which is limited to the initialization phase (Local Allocation Strategy (comp_req__log__local_allocation_strategy)) |
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Slot handling |
Bounded loops (No Endless Loops (comp_req__log__no_endless_loops)) |
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File output backend |
Not for production use, it uses a mutex in |
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Syslog backend, slog backend |
Syslog on Linux only, slog on QNX only |
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Datarouter backend |
Size limit of a shared memory entry, larger entries are dropped and counted |
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Datarouter backend |
Size limit of messages and notifications, input from the Datarouter is untrusted |
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Datarouter backend |
Dynamic identifier mode for testing only |
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External Dependencies#
External dependencies and their relationships are defined in the Bazel BUILD
targets.
FFI classifications are maintained using Bazel target metadata,
including the FFI tag.
The dependency tree used for implementation inspection and
safety analysis is generated from the Bazel dependency graph.
Rationale Behind Decomposition into Units#
The component is split by output channel so that each unit has a single
responsibility and can be tested and selected independently. The units and
their relations are shown in mw_log_recorders.puml in
Static Diagrams for Unit Interactions.
Static Diagrams for Unit Interactions#
The backend composition and recorder relationships are shown below:
Further static diagrams are part of the unit documents listed under Units within the Component.
Dynamic Diagrams for Unit Interactions#
The sequence of one log call through the syslog backend is shown below. Further dynamic views (sequence diagrams) are part of the unit documents listed under Units within the Component.
Units within the Component#
The decomposition into units is given by the directory and file structure; a unit
belongs to this component through its location. Attributes, behavior and the
interfaces of a unit are documented in the source code (public headers). Paths are
relative to score/mw/log of this repository unless noted otherwise.
Interfaces of the Component#
The architecture interfaces are realized by the source code interfaces shown in the diagrams. The interface documentation is part of the headers.
Architecture interface |
Diagram |
|---|---|
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Control Channel (logic_arc_int__logging__session_ctrl_channel) |
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Inspection Checklist#
The checklist for verification of the detailed design and code can be found here: