Memory Shared Component Architecture

Memory Shared		status: valid security: YES safety: ASIL_B
belongs to: feat__baselibs has: comp_arc_sta__baselibs__memory_shared, comp_req__memory__shared_memory, comp_req__memory__offset_ptr, comp_req__memory__shared_container, comp_req__memory__inter_process_sync, comp_req__memory__bounds_check, comp_req__memory__endianness, comp_req__memory__sealed_shm, comp_req__memory__typed_memory, comp_req__memory__resource_registry, comp_req__memory__string_utils, comp_req__memory__atomic_ops, comp_req__memory__deterministic_alloc, comp_req__memory__address_independence implements: logic_arc_int__baselibs__memory_shared uses: logic_arc_int__os__fcntl, logic_arc_int__os__stat, logic_arc_int__os__mman included by: mod__baselibs, mod_view_sta__baselibs__baselibs
comp__baselibs_memory_shared		Component

Memory Shared Static view		status: valid security: YES safety: ASIL_B
belongs to: comp__baselibs_memory_shared fulfils: comp_req__memory__shared_memory, comp_req__memory__offset_ptr, comp_req__memory__shared_container, comp_req__memory__inter_process_sync, comp_req__memory__bounds_check, comp_req__memory__endianness, comp_req__memory__sealed_shm, comp_req__memory__typed_memory, comp_req__memory__resource_registry, comp_req__memory__string_utils, comp_req__memory__atomic_ops, comp_req__memory__deterministic_alloc, comp_req__memory__address_independence
comp_arc_sta__baselibs__memory_shared		Component Package Diagram

Open		status: valid security: YES safety: ASIL_B
included by: logic_arc_int__baselibs__memory_shared
logic_arc_int_op__baselibs__open		Logical Interface Operation

Update		status: valid security: YES safety: ASIL_B
included by: logic_arc_int__baselibs__memory_shared
logic_arc_int_op__baselibs__update		Logical Interface Operation

Lock		status: valid security: YES safety: ASIL_B
included by: logic_arc_int__baselibs__memory_shared
logic_arc_int_op__baselibs__lock		Logical Interface Operation

Set Permissions		status: valid security: YES safety: ASIL_B
included by: logic_arc_int__baselibs__memory_shared
logic_arc_int_op__baselibs__set_perm		Logical Interface Operation